1. Field of the Invention
The present invention relates to a Schmitt circuit implemented using insulated gate field effect transistors, referred to as MOS transistors in the present application, and more specifically to a Schmitt circuit capable of maintaining with accuracy a threshold voltage thereof.
2. Description of the Prior Art
Conventionally a Schmitt circuit was integrated in an integrated circuit such as a large scale integration in the manner as shown in FIG. 1.
The Schmitt circuit shown in FIG. 1 comprises a series connection of a first, second and third MOS transistors 1', 2' and 3' interposed between a voltage source V.sub.DD and the ground, and a fourth MOS transistor 4' coupled between the voltage source V.sub.DD and the junction of the second and third MOS transistors 2' and 3'. The drain and the gate of the first MOS transistor 1' are connected to the voltage source V.sub.DD 5 so that the first MOS transistor 1' functions as a so-called load MOS transistor, while the source of the first MOS transistor 1' is connected to the drain of the second MOS transistor 2' and the gate of the fourth MOS transistor 4', where an output voltage V.sub.OUT is withdrawn. On the other hand, the input voltage V.sub.IN is applied to the gates of the second and third MOS transistors 2' and 3' and the junction of the source of the second MOS transistor 2' and the drain of the third MOS transistor 3' is connected to the source of the fourth MOS transistor 4'. The MOS transistors 1', 2' and 3' and 4' may be N-channel MOS transistors formed on the same pellet.
Now an operation of the Schmitt circuit shown in FIG. 1 will be described with reference to FIG. 2. FIG. 2 is a graph showing a relation between the input voltage V.sub.IN in the abscissa and the voltages at the respective portions in the ordinate. In the graph, Vt1, Vt2, Vt3 and Vt4 denote threshold voltages of the MOS transistors 1', 2', 3' and 4', and .DELTA.Vt1, .DELTA.Vt2 and .DELTA.Vt4 denote backgate bias voltages of the first, second and fourth MOS transistors 1', 2' and 4'. In general, the region where the channels of MOS transistors are formed, i.e. the substrate is connected to the ground and a backgate bias voltage is applied by the voltage developed between the substrate and the source.
When the input voltage V.sub.IN is zero volt, the second and the third MOS transistors 2' and 3' are turned off, while when the source voltage V1 of the first MOS transistor 1' is lower than V.sub.DD -(Vt1+.DELTA.Vt1) the first MOS transistor 1' is turned on, thereby to raise the voltage V1 to the V.sub.DD -(Vt1+.DELTA.Vt1). Accordingly, the gate of the fourth MOS transistor 4' is supplied with the voltage V1 of the V.sub.DD -(Vt1+.DELTA.Vt1). On the other hand, when the source voltage V2 of the fourth MOS transistor 4' is lower than V1-(Vt4+.DELTA.Vt4), i.e. V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4), the fourth MOS transistor 4' is turned on, thereby to raise the voltage V2 to V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4). More specifically, when the input voltage V.sub.IN is zero volt, the relations of V1=V.sub.DD -(Vt1+.DELTA.Vt1), V2=(V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4) are established.
When the input voltage V.sub.IN increases and exceeds the threshold voltage Vt3 of the third MOS transistor 3', the third MOS transistor 3' starts turning on, whereby a current flows through the fourth MOS transistor 4'. Normally the third and fourth MOS transistors 3' and 4' are fabricated in the same size. In such a case, as the input voltage V.sub.IN increases the voltage V2 decreases along an auxiliary line (a) having the angle of 45.degree. with respect to the abscissa from the voltage of V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4). When the difference between the input voltage V.sub.IN and the voltage V2 coincides with Vt2+.DELTA.Vt2, i.e. when the auxiliary lines (a) and (b) intersects each other, the second MOS transistor 2' is turned on and the voltage V1 decreases. Therefore, the voltage V2 also decreases and the voltage between the gate and the source of the second MOS transistor 2' increases, whereby the voltage V1 further decreases due to a feedback function, with the result that the voltages V1 and V2 abruptly fall to the vicinity of the ground level, whereby it is supposed that the fourth MOS transistor 4' is turned off. However, the backgate bias voltages .DELTA.Vt2 and .DELTA.Vt4 decrease by dVt due to the fact that the source voltage V2 decreases. Accordingly, in actuality the voltage V2 changes along a locus of the gradient smaller than 45.degree. with respect to the abscissa, while the voltage obtained by substracting (Vt2+.DELTA.Vt2) from the input voltage V.sub.IN, i.e. V.sub.IN -(Vt2+.DELTA.Vt2) falls as shown by an auxiliary line (c) having the angle more than 45.degree. with respect to the abscissa starting from the time point when the input voltage V.sub.IN becomes equal to Vt3. The input voltage V.sub.IN when the voltage V2 and the auxiliary line (c) intersect each other becomes the threshold voltage V.sub.TH of the Schmitt circuit, the voltage V.sub.TH being also consistent with the auxiliary lines (a) and (b). The reason is that since the source voltage V2 of the second and fourth MOS transistors 2' and 4' is common the difference dVt of the backgate bias voltages .DELTA.Vt2 and .DELTA.Vt4 is offset, whereby no influence is caused to the threshold voltage V.sub.TH of the Schmitt circuit.
In the case where the input voltage V.sub.IN falls from a sufficiently high voltage, when the potential difference between the input voltage V.sub.IN and the voltage V2 becomes smaller than the sum {Vt2+.DELTA.Vt2(V2)} of the threshold voltage Vt2 of the MOS transistor 2' and the backgate bias voltage .DELTA.Vt2(V2) at the voltage V2 at that time, i.e. when the auxiliary line (c) and the voltage V2 intersect each other, the second MOS transistor 2' is turned off and the voltage V1 returns to the initial voltage V.sub.DD -(Vt1+.DELTA.Vt1) and at the same time the fourth MOS transistor 4' is again turned on, whereby the voltage V2 changes along the predetermined locus. When the input voltage V.sub.IN becomes smaller than the threshold voltage Vt3 of the third MOS transistor 3', the MOS transistor 3' is turned off and the voltage V2 returns to the initial voltage V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4).
Referring to FIG. 2, if the auxiliary lines (d) and (e) are drawn at the angle of 45.degree. with respect to the abscissa from the intersection of the locus of the voltage V2 and the auxiliary line (c), a half of the voltage between the points where these intersect the ordinate becomes the threshold voltage V.sub.TH of the Schmitt circuit. More specifically, the threshold voltage V.sub.TH of the Schmitt circuit may be expressed by the following equation. ##EQU1##
Since the MOS transistors 1', 2', 3' and 4' are all formed on the same chip, the threshold voltages Vt1, Vt2, Vt3 and Vt4 of the MOS transistors become equal to each other, while the backgate bias voltages .DELTA.Vt2 and .DELTA.Vt4 are also equal to each other because the sources thereof are common. Accordingly, the threshold voltage V.sub.TH of the Schmitt circuit may be expressed by the following equation. ##EQU2##
As is clear from the foregoing equation, the threshold voltage V.sub.TH of the Schmitt circuit becomes smaller than a half of the source voltage V.sub.DD by a half of the backgate bias voltage .DELTA.Vt1 of the first MOS transistor 1', resulting in the shortcoming that accurate regulation to the source voltage V.sub.DD can not be achieved. Furthermore a further shortcoming was involved that in the case where the input voltage V.sub.IN remains zero volt for a long period of time, the point of the voltage V1 becomes a floating state and the first MOS transistor 1' enters in the off region due to an ordinary noise and a leak current, whereby the voltage V1 becomes higher than V.sub.DD -(Vt1+.DELTA.Vt1) and becomes unstable, while the voltage V2 also becomes higher than V.sub.DD -(Vt1+.DELTA.Vt1)-(Vt4+.DELTA.Vt4), with the result that the threshold voltage V.sub.TH of the Schmitt circuit becomes unstable.